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ATmega128
TWI Register
Description
TWI Bit Rate Register
– TWBR
Bit
Read/ W rite
Initial Value
7
TWBR7
R/ W
0
6
TWBR6
R/ W
0
5
TWBR5
R/ W
0
4
TWBR4
R/ W
0
3
TWBR3
R/ W
0
2
TWBR2
R/ W
0
1
TWBR1
R/ W
0
0
TWBR0
R/ W
0
TWBR
? Bits 7..0 – TWI Bit Rate Register
T W BR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator
Unit” on page 203 for calculating bit rates.
TWI Control Register –
TWCR
Bit
Read/ W rite
Initial Value
7
TWINT
R/ W
0
6
TWEA
R/ W
0
5
TWSTA
R/ W
0
4
TWSTO
R/ W
0
3
TWWC
R
0
2
TWEN
R/ W
0
1
–
R
0
0
TWIE
R/ W
0
TWCR
The T W CR is used to control the operation of the T W I. It is used to enable the T W I, to initiate a
master access by applying a START condition to the bus, to generate a receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the T W DR. It also indicates a write collision if data is attempted written to
T W DR while the register is inaccessible.
? Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the T W I has finished its current job and expects application
software response. If the I-bit in SREG and T W IE in T W CR are set, the MCU will jump to the
T W I interrupt vector. W hile the T W INT flag is set, the SCL low period is stretched.
The T W INT flag must be cleared by software by writing a logic one to it. Note that this flag is not
automatically cleared by hardware when executing the interrupt routine. Also note that clearing
this flag starts the operation of the T W I, so all accesses to the T W I Address Register (T W AR),
T W I Status Register (T W SR), and T W I Data Register (T W DR) must be complete before clearing
this flag.
? Bit 6 – TWEA: TWI Enable Acknowledge Bit
The T W EA bit controls the generation of the acknowledge pulse. If the T W EA bit is written to
one, the ACK pulse is generated on the T W I bus if the following conditions are met:
1. The device’s own slave address has been received.
2. A general call has been received, while the T W GCE bit in the T W AR is set.
3. A data byte has been received in Master Receiver or Slave Receiver mode.
By writing the T W EA bit to zero, the device can be virtually disconnected from the Two-wire
Serial Bus temporarily. Address recognition can then be resumed by writing the T W EA bit to one
again.
? Bit 5 – TWSTA: TWI START Condition Bit
The application writes the T W STA bit to one when it desires to become a master on the Two-
wire Serial Bus. The T W I hardware checks if the bus is available, and generates a START con-
dition on the bus if it is free. However, if the bus is not free, the T W I waits until a STOP condition
is detected, and then generates a new START condition to claim the bus Master status. T W STA
must be cleared by software when the START condition has been transmitted.
205
2467X–AVR–06/11
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